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edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development description this is a family of 1048576-word by 4-bit dynamic rams, fabricated with the high performance cmos process,and is ideal for large- capacity memory systems where high speed, low power dissipation, and low costs are essential. the use of quadruple-layer polysilicon process combined with silicide technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. multiplexed address inputs permit both a reduction in pins and an increase in system densities. self or extended refresh current is low enough for battery back-up application. application main memory unit for computers, microcomputer memory, refresh memory for crt, frame buffer memory for crt 1 edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis standard 26 pin soj, 26 pin tsop(ii) single 5v?0%supply low stand-by power dissipation cmos lnput level 5.5mw (max) * cmos lnput level 550? (max) low operating power dissipation m5m44405cxx-5,-5s 687.5mw (max) m5m44405cxx-6,-6s 550.0mw (max) m5m44405cxx-7,-7s 467.5mw (max) self refresh capabiility * self refresh current 120?(max) extended refresh capability * extended refresh current 120?(max) hyper-page mode (1024-bit random access), read-modify- write, ras-only refresh cas before ras refresh, hidden refresh, cbr self refresh(-5s,-6s,-7s) capabilities early-write mode and oe and w to control output buffer impedance all inputs, output ttl compatible and low capacitance 1024 refresh cycles every 16.4ms (a 0 ~a 9 ) 1024refresh cycle every 128ms (a 0 ~a 9 ) * 4-bit parallel test mode capability * : applicable to self refresh version (m5m44405cj,tp-5s,-6s,-7s : option) only features xx=j,tp m5m44405cxx-7,-7s m5m44405cxx-6,-6s 60 70 15 20 30 35 110 130 400 350 15 20 m5m44405cxx-5,-5s 50 13 25 90 500 13 cas access time oe access time type name ras access time (max.ns) (max.ns) (max.ns) address access time (min.ns) cycle time power dissipa- tion (typ.mw) (max.ns) pin description a 0 ~a 9 dq 1 ~dq 4 ras w vcc vss cas oe pin name function address inputs data inputs / outputs row address strobe input column address strobe input write control input power supply (+5v) ground (0v) output enable input pin configuration (top view) outline 26p0j (300mil soj) 1 9 2 3 4 5 11 10 12 13 26 25 24 23 22 16 18 17 15 14 dq 1 dq 2 a 0 a 1 a 2 a 3 v cc v ss dq 4 dq 3 cas oe a 9 a 8 a 7 a 6 a 5 a 4 w ras outline 26p3z-e (300mil tsop) 1 9 2 3 4 5 11 10 12 13 26 25 24 23 22 16 18 17 15 14 dq 1 dq 2 a 0 a 1 a 2 a 3 v cc v ss dq 4 dq 3 cas oe a 9 a 8 a 7 a 6 a 5 a 4 w ras
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development function the m5m44405cj, tp provide, in addition to normal read, write, and read-modify-write operations,a number of other functions, e.g., hyper page mode, ras-only refresh, and delayed-write. the input conditions for each are shown in table 1. table 1 input conditions for each mode block diagram operation read write (early write) write (delayed write) read-modify-write ras-only refresh cas before ras refresh stand-by hidden refresh self refresh * ras cas oe inputs input/output refresh remark w row address address column input output act act act act act act act nac act act act act nac act act dnc nac act act act dnc dnc nac dnc act dnc nac act dnc act dnc dnc apd apd apd apd apd dnc dnc dnc apd apd apd apd dnc dnc dnc dnc opn apd apd apd dnc opn dnc dnc vld opn ivd vld opn vld opn opn yes yes yes yes yes yes yes no hyper- page mode identical act act nac dnc dnc dnc dnc opn yes note : act : active, nac : nonactive, dnc : don' t care, vld : valid, ivd : invalid, apd : applied, opn : open column decoder sense refresh amplifer & i /o control row decoder memory cell (4,194,304 bits) v cc (5v) v ss (0v) dq 1 dq 2 dq 3 dq 4 oe data inputs / outputs output enable input clock generator circuit (4) data in buffers (4) data out buffers a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 address inputs row & column address buffer column address strobe input row address strobe input write control input cas ras w a 0 ~a 9 a 0 ~ a 9
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development note 2 : current flowing into an ic is positive, out is negative. note 3 : i cc1(av) , i cc3 (av) , i cc4(av) and i cc6(av) are dependent on cycle rate. maximum current is measured at the fastest cycle rate. note 4 : i cc1(av) and i cc4(av) are dependent on output loading. specified values are obtained with the output open. note 5 : column address can be changed once or less while ras=v il and cas=v ih . 3 absolute maximum ratings v cc v i v o i o p d t opr t stg v v v ma mw - 1~7 50 1000 0~70 - 65~150 ta=25?c - 1~7 - 1~7 ?c ?c recommended operating conditions (ta=0~70?c, unless otherwise noted) (note 1) v v v v 5.5 0 6.0 0.8 5 0 4.5 0 2.4 - 1.0 v cc v ss v ih v il 0.8 - 2.0 dq 1 ~ 4 electrical characteristics (ta=0~70?c, v cc = 5v?0%, v ss =0v, unless otherwise noted) (note 2) v oh v ol i oz i i i cc1 (av) i cc2 (av) i cc3 (av) i cc4(av) i cc6(av) i cc8(av) i cc9(av) m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s i oh =?ma i ol = 4.2ma q floating 0v v out 5.5v 0v v in +6.5v, other inputs pins= 0v ras, cas cycling t rc =t wc =min. output open ras= cas =v ih , output open ras= cas 3 v cc ?.5v output open ras cycling, cas= v ih t rc =min. output open ras=v il , cas cycling t pc =min. output open cas before ras refresh cycling t rc =min. output open v v ? ma ma ma ma ma ras cycling cas 0.2v or cas before ras refresh cycling ras 0.2v or 3 v cc -0.2v cas 0.2v or 3 v cc -0.2v w 0.2v(except for ras falling edge) or v cc -0.2v oe 0.2v or 3 v cc -0.2v a 0 ~a 9 0.2v or 3 v cc -0.2v, dq=open t rc =125?, t ras = t ras min ~1? ras=cas 0.2v output open ? ? symbol parameter conditions ratings unit with respect to vss supply voltage input voltage output voltage output current power dissipation operating temperature storage temperature v symbol parameter unit limits min nom max supply voltage supply voltage high-level input voltage, all inputs low-level input voltage others note 1 : all voltage values are with respect to vss. ? m5m44405c m5m44405c(s) symbol parameter limits min max unit typ test conditions vcc 0.4 10 10 125 2 1 2.4 0 -10 -10 85 120 120 0.1 100 125 85 100 105 75 85 125 85 100 high-level output voltage low-level output voltage off-state output current input current average supply current from vcc, operating (note 3,4,5) supply current from vcc , stand-by (note 6) average supply current from vcc, refreshing (note 3,5) average supply current from vcc, hyper-page- mode (note 3,4,5) average supply current from vcc, cas before ras refresh mode (mote 3) average supply current from vcc, extended-refresh cycle (note 6) average supply current from vcc, self-refresh cycle (note 6) m5m44405c(s)
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development note 6 : an initial pause of 200? is required after power-up followed by a minimum of eight initialization cycles (ras only refresh or cas before ras refresh cycles). note the ras may be cycled during the initial pause . and eight initialization cycles are required after prolonged periods (greater than t ref(max) ) of ras inactivity before proper device operation is achieved. note 7 : measured with a load circuit equivalent to 2ttl and 100pf. the reference levels for measuring of output signals are 2.0v(v oh ) and 0.8v(v ol ). note 8 : assumes that t rcd 3 t rcd(max) and t asc 3 t asc(max) and t cp 3 t cp(max) . note 9 : assumes that t rcd t rcd(max) and t rad t rad(max) . if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac will increase by amount that t rcd exceeds the value shown. not 10 : assumes that t rad 3 t rad(max) and t asc t asc(max) . no t 11 : assumes that t cp t cp(max) and t asc 3 t asc(max) . no t 12 : t oez(max) , t wez(max) , t off(max) and t rez(max) defines the time at which the output achieves the high impedance state (i out ?0? ) and is not reference to v oh(min) or v ol(max) . not 13 : output is disabled after both ras and cas go to high. capacitance (ta=0~70?c, v cc = 5v?0%, v ss =0v, unless otherwise noted) pf pf pf c i (a) c i (clk) c i / o 5 7 7 v i =v ss f=1mhz v i =25mvrms switching characteristics (ta=0~70?c, v cc = 5v?0%, v ss =0v, unless otherwise noted, see notes 6,14,15) t cac t rac t aa t cpa t oea t clz t oez t off ns ns ns ns 30 33 60 25 28 50 15 13 35 38 70 20 5 5 15 13 ns ns 13 15 ns 5 20 20 ns 15 13 20 m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s ns ns t wez t rez 15 13 13 15 20 20 t ohc t ohr 5 5 ns 5 5 5 ns 5 4 limits min max unit typ symbol parameter test conditions parameter symbol limits unit min max min max min max input capacitance, address inputs input capacitance, clock inputs input/output capacitance, data ports access time from cas access time from ras column address access time access time from cas precharge (note 7,8) (note 7,9) (note 7,10) (note 7,11) (note 7) access time from oe (note 12) output disable time after oe high output disable time after we high output disable time after cas high output disable time after ras high (note 12) (note 12,13) (note 12,13) output low impedance time from cas low (note 7) output hold time from cas output hold time from ras (note 13)
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development timing requirements (for read, write, read-modify-write, refresh, and hyper-page mode cycles) (ta=0~70?c, v cc = 5v?0%, v ss =0v, unless otherwise noted, see notes 14,15) m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s parameter symbol limits unit min max min max min max t ref t ref t rp t rcd t crp t rpc t cpn t rad t asr t asc t rah t cah t dzc t dzo t rdd t cdd t odd t t note 14 : the timing requirements are assumed t t =2ns. note 15 : v ih(min) and v il(max) are reference levels for measuring timing of input signals. note 16 : t rcd(max) is specified as a reference point only. if t rcd is less than t rcd(max), access time is t rac . if t rcd is greater than t rcd(max) , access time is controlled exclusively by t cac or t aa . note 17 : t rad(max) is specified as a reference point only. if t rad 3 t rad(max) and t asc t asc(max) , access time is controlled exclusively by t aa . note 18 : t asc(max) is specified as a reference point only. if t rcd 3 t rcd(max) and t asc 3 t asc(max) , access time is controlled exclusively by t cac . note 19 : either t dzc or t dzo must be satisfied. note 20 : either t rdd or t cdd or t odd must be satisfied. note 21 : t t is measured between v ih(min) and v il(max) . refresh cycle time ras high pulse width delay time, ras low to cas low delay time, cas high to ras low delay time, ras high to cas low cas high pulse width (note 21) (note 16) (note 17) (note 18) 16.4 45 30 0 40 13 50 20 5 10 15 10 10 0 0 1 16.4 37 25 0 30 10 50 18 5 8 13 8 8 0 0 1 column address delay time from ras low row address setup time before ras low column address setup time before cas low row address hold time after ras low column address hold time after cas low transition time (note 19) (note 20) (note 19) (note 20) delay time, data to cas low delay time, data to oe low delay time, cas high to data delay time, oe high to data 0 0 0 0 15 13 15 13 128 128 (note 20) delay time, ras high to data 15 13 ms ms ns ns ns ns ns ns ns ns ns 16.4 50 35 0 50 13 50 20 5 13 15 10 10 0 0 1 0 0 20 20 128 20 ns ns ns ns ns ns ns refresh cycle time * read and refresh cycles t rc t ras t cas t csh t rsh t rcs t rch t rrh t ral t cal t orh t och m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s parameter symbol limits unit min max min max min max read cycle time ras low pulse width cas low pulse width cas hold time after ras low read setup time before cas low read hold time after cas high (note 22) (note 22) ras hold time after cas low read hold time after ras high column address to ras hold time ras hold time after oe low column address to cas hold time cas hold time after oe low note 22 : either t rch or t rrh must be satisfied for a read cycle. 0 0 10000 10000 10000 10000 90 50 8 40 13 25 13 0 0 110 60 10 48 15 30 15 13 18 ns ns ns ns ns ns ns ns ns ns ns 10000 10000 0 0 130 70 13 55 20 35 20 23 13 15 ns 20 0 0 0 5
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development write cycle (early write and delayed write) m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s parameter symbol limits unit min max min max min max 8 0 10000 10000 10000 10000 90 50 8 40 13 8 8 8 0 10 0 110 60 10 48 15 10 10 10 0 8 10 ns ns ns ns ns ns ns ns ns ns ns 10000 10000 13 0 130 70 13 55 20 13 13 13 0 13 ns write cycle time ras low pulse width cas low pulse width cas hold time after ras low write setup time before cas low write hold time after cas low (note 24) ras hold time after cas low cas hold time after w low ras hold time after w low data setup time before cas low or w low data hold time after cas low or w low write pulse width t wc t ras t cas t csh t rsh t wcs t wch t cwl t rwl t wp t ds t dh m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s parameter symbol limits unit min max min max min max read-write and read-modify-write cycles t rwc t ras t cas t csh t rsh t rcs t cwd t rwd t awd t oeh note 23 : t rwc is specified as t rwc(min) = t rac(max) + t odd(min) + t rwl(min) + t rp(min) +4 t t . note 24 : t wcs , t cwd , t rwd and t awd and, t cpwd are specified as reference points only. if t wcs 3 t wcs(min) the cycle is an early write cycle and the dq pins will remain high impedance throughout the entire cycle. if t cwd 3 t cwd(min) , t rwd 3 t rwd(min) , t awd 3 t awd(min) and t cpwd 3 t cpwd(min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the dq will contain the data read from the selected address. if neither of the above condition (delayed write) of the dq (at access time and until cas or oe goes back to v ih ) is indeterminate. 44 44 0 32 77 47 38 109 38 75 0 28 65 40 10000 10000 10000 10000 75 133 89 89 ns ns ns ns ns ns ns ns ns 57 57 0 42 92 57 10000 10000 161 107 107 13 15 20 ns read write/read modify write cycle time ras low pulse width cas low pulse width cas hold time after ras low ras hold time after cas low read setup time before cas low (note 23) (note 24) delay time, cas low to w low delay time, ras low to w low delay time, address to w low (note 24) (note 24) oe hold time after w low 6
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development hyper page mode cycle (read, early write, read-write, read-modify-write cycle, read write mix cycle, hi-z control by oe or w) (note 25) t hpc t hprwc t doh t ras t cp t cprh t cpwd t chol t oepe t wpe t hcwd t hawd t hpwd t hcod t haod t hpod m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s parameter symbol limits unit min max min max min max hyper page mode read/write cycle time ras low pulse width for read or write cycle cas high pulse width ras hold time after cas precharge (note 26) (note 28) delay time, cas precharge to w low (note 24) hyper page mode read write/read modify write cycle time hold time to maintain the data hi-z until cas access oe pulse width (hi-z control) w pulse width (hi-z control) output hold time from cas low delay time, cas low to w low after read delay time, address to w low after read delay time, cas precharge to w low after read delay time, cas low to oe high after read delay time, address to oe high after read delay time, cas precharge to oe high after read 28 20 65 8 43 100000 33 25 77 10 50 100000 13 16 57 66 7 7 7 7 7 7 ns ns ns ns ns ns ns ns ns 38 30 92 13 60 100000 16 79 7 7 7 ns 5 5 5 ns ns ns ns ns ns 28 32 42 40 47 57 43 50 60 13 15 20 25 30 35 28 33 38 (note 27) note 25 : all previously specified timing requirements and switching characteristics are applicable to their respective hyper page mode cycle. note 26 : t hpc(min) is specified in the case of read-only and early write-only in hyper page mode. note 27 : t ras(min) is specified as two cycles of cas input are performed. note 28 : t cp(max) is specified as a reference point only. m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s parameter symbol limits unit min max min max min max t csr t chr t rsr t rhr t cas cas before ras refresh cycle (note 29) cas setup time before ras low cas hold time after ras low read setup time before ras low read hold time after ras low cas low pulse width 5 10 5 10 ns ns 5 15 ns 10 10 10 ns 10 10 15 ns 17 17 22 m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s parameter symbol limits unit min max min max min max self refresh cycle * (note 30) t rass t rps t chs t rsr t rhr cbr self refresh ras low pulse width cbr self refresh ras high precharge time cbr self refresh cas hold time read setup time before ras low read hold time after ras low 100 - 50 90 100 - 50 110 ns ns ns 100 - 50 130 ns 10 10 10 ns 10 10 15 note 29 : eight or more cas before ras cycles instead of eight ras cycles are necessary for proper operation of cas before ras refresh mode. 7
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development 8 test mode specification (note 31) electrical characteristics (ta=0~70?c, v cc = 5v?0%, v ss =0v, unless otherwise noted) (note 2) i cc1(av) i cc3(av) i cc4(av) i cc6(av) average supply current from v cc, operating (note 3,4,5) average supply current from v cc, refreshing (note 3,5) average supply current from vcc, hyper-page- mode (note 3,4,5) average supply current from v cc, cas before ras refresh mode (note 3) m5m44405c-5,-5s m5m44405c-7,-7s m5m44405c-6,-6s m5m44405c-5,-5s m5m44405c-7,-7s m5m44405c-6,-6s m5m44405c-5,-5s m5m44405c-7,-7s m5m44405c-6,-6s m5m44405c-5,-5s m5m44405c-7,-7s m5m44405c-6,-6s ras, cas cycling t rc =t wc =min. output open ras cycling, cas=v ih t rc =min. output open ras=v il , cas cycling t pc =min. output open cas before ras refresh cycling t rc =min. output open ma ma ma ma 145 115 145 115 145 120 85 100 100 115 100 100 symbol parameter limits min max unit typ test conditions note 31 : all previously specified electrical characteristics, switing characteristics, and timing requirements are applicable to that of test mode. switching characteristics (ta=0~70?c, v cc = 5v?0%, v ss =0v, unless otherwise noted, see notes 6,14,15) t cac t rac t aa t cpa t oea ns ns ns ns ns 20 35 38 65 18 30 33 55 20 18 25 40 43 75 25 access time from cas access time from ras column address access time access time from cas precharge (note 7,8) (note 7,9) (note 7,10) (note 7,11) (note 7) access time from oe symbol parameter limits min max unit min max min max m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s symbol parameter limits min max unit min max min max m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s t rc t ras t cas t csh t rsh t ral t cal t orh t och timing requirements (ta=0~70?c, v cc = 5v?0%, v ss =0v, unless otherwise noted, see notes 14,15) read and refresh cycles read cycle time ras low pulse width cas low pulse width cas hold time after ras low ras hold time after cas low column address to ras hold time ras hold time after oe low 10000 10000 10000 10000 95 55 13 45 18 30 18 115 65 15 53 20 35 20 column address to cas hold time 18 23 ns ns ns ns ns ns ns ns 10000 10000 135 75 18 60 25 40 25 28 cas hold time after oe low 18 20 ns 25 symbol parameter limits min max unit min max min max m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s t rwc t ras t cas t csh t rsh t cwd t rwd t awd read-write and read-modify-write cycles read write/read modify write cycle time ras low pulse width cas low pulse width cas hold time after ras low ras hold time after cas low (note 23) (note 24) 49 49 37 82 52 43 114 43 80 33 70 45 delay time, cas low to w low delay time, ras low to w low delay time, address to w low (note 24) (note 24) 10000 10000 10000 10000 80 138 94 94 ns ns ns ns ns ns ns ns 62 62 47 97 62 10000 10000 166 112 112
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development 9 hyper page mode cycle (read, early write, read-write, read-modify-write cycle, read write mix cycle, hi-z control by oe or w) (note 25) t hpc t hprwc t ras t cprh t cpwd t hcwd t hawd t hpwd t hcod t haod t hpod hyper page mode read/write cycle time ras low pulse width for read or write cycle ras hold time after cas precharge (note 26) delay time, cas precharge to w low (note 24) hyper page mode read write/read modify write cycle time delay time, cas low to w low after read delay time, address to w low after read delay time, cas precharge to w low after read delay time, cas low to oe high after read delay time, address to oe high after read delay time, cas precharge to oe high after read 33 25 70 48 100000 38 30 82 55 100000 62 71 ns ns ns ns ns 43 35 97 65 100000 84 ns ns ns ns ns ns 33 37 47 45 52 62 48 55 65 18 20 25 30 35 40 33 38 43 (note 27) symbol parameter limits min max unit min max min max m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s symbol parameter limits min max unit min max min max m5m44405c-5,-5s m5m44405c-6,-6s m5m44405c-7,-7s write setup time before ras low write hold time after ras low 10 10 10 10 ns ns 10 15 t wsr t whr test mode set cycle
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development timing diagram (note 32) read cycle t crp t asr t rah t rad t rcd t csh t asc t cah t ras t rc t rsh t cas t ral t cac t aa t clz t rac t off t rch t rrh t asr t rp row address note 32 indicates the don't care input. v ih(min) v in v ih(max) or v il(min) v in v il(max) indicates the invalid output. t dzc hi-z t oez t odd t oea t och t dzo t orh t crp hi-z 10 hi-z t cal t wez t rez t ohc t ohr t oho row address t rcs data valid column address t cdd dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development early write cycle t crp t asr t rah t rcd t csh t asc t cah t wcs t ras t wc t rsh t cas t wch t asr t crp t rp hi-z row address data valid row address column address t ds t dh 11 dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development delayed write cycle t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t wc t rsh t cas t asr t crp t rp column address row address data valid row address t clz t wch t cwl t rwl t dh t ds hi-z t wp t dzc t oez t dzo t odd t oeh hi-z hi-z 12 t oho dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development read-write, read-modify-write cycle t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t rwc t rsh t cas t asr t crp t rp row address data valid column address t clz t cwl t rwl t dh t ds hi-z hi-z t wp t dzc t oez t dzo t odd t oeh t awd t cwd t rwd data valid t aa t cac t rac t oea t rad hi-z 13 t oho row address dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development hyper page mode read cycle t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr t rp t cas t asc t dzo t oea t och t csh t hpc t cas t cp t cas t rsh t cah t asc t cah t asc t ral t rch t cdd t cpa t odd t rez t off t clz t doh t rdd t cac t aa t cpa t doh t cac t cal t cal t cal t ohc t ohr t wez row address hi-z 14 hi-z column-3 column-2 t cprh column-1 row address t rcs t dzc t rrh t oez t oho data valid-3 data valid-2 data valid-1 t aa dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development hyper page mode early write cycle t crp t asr t rah t rcd t cah t ras t cp t asr t rp t cas t asc t wcs t csh t hpc t cas t cp t cas t rsh t cah t cah t asc t asc t wch t wcs t wch t wcs t wch t ds t dh t ds t dh t ds t dh t cal t cal t crp data valid-1 row address row address data valid-2 data valid-3 hi-z 15 column-1 column-2 column-3 dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development hi-z hyper page mode read-write, read-modify-write cycle t crp t asr t rah t rcd t cah t ras t cp t asr t rp t cas t asc t csh t hprwc t cas t rwl t cah t asc t rcs t rwd t ds t cwl t wp t rcs t wp t cwl hi-z t dh t ds t dzc t cpwd t dh t clz t dzo t oez t odd t oez t oeh t rad t cwd t awd t awd t cwd t cac t aa t cac t rac t oea t dzo t cpa t oea t odd t oho t oho t crp row address 16 hi-z hi-z row address column-1 column-2 t dzc hi-z t aa t clz dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il data valid-1 data valid -1 data valid -2 data valid-2
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development t wch t dh hyper page mode mix cycle (1) t crp t asr t rah t rad t rcd t cah t ras t cp t cac t rac t rp t cas t asc t dzo t oea t och t csh t hpc t cas t cp t cas t cah t asc t cah t asc t hprwc t cpwd t wp t ds t clz t cpa t cal t cal t cwd t oez t odd t wez t oeh t oez t oea t asr t crp t cac t odd t dh t ds t rwl t cwl t dzo t awd 17 hi-z row address column-1 row address t dzc t rcs column-2 t wcs column-3 t dzc t aa t aa t clz t oho t oho dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il data valid -3 data valid-3 data valid -1 data valid-2
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development t cah t asc t aa t cac t oez t ds t odd t dh t dzc t cah t asc t cah t asc t cpa t aa t wch t cac t oea t clz t cpa t cal t cp t cas t rch t wcs t wez t cal t oho t dzc t cas t hcod t haod t hpod t hcwd t hawd t hpwd hyper page mode mix cycle (2) hi-z hi-z hi-z 18 column-1 column-2 column-3 dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il data valid-2 data valid-1 data valid-3
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr t rp t cas t asc t dzo t oea t csh t hpc t cas t cp t cas t rsh t cah t asc t cah t asc t ral t rch t cdd t cpa t odd t rez t off t clz t doh t rdd t cac t aa t cpa t oez t cac t aa hyper page mode read cycle ( hi-z control by oe ) t clz t oepe t chol t oepe t oez t oea t ohr t ohc t oho t oho t crp t wez column-1 column-2 hi-z row address row address data valid-3 hi-z hi-z 19 t cprh column-3 t rrh t rcs t och t oez t oho t dzc dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il data valid-1 data valid-1 data valid-2
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr t rp t cas t asc t dzo t oea t och t csh t hpc t cas t cp t cas t rsh t cah t asc t cah t asc t ral t rch t cdd t cpa t odd t rez t clz t doh t rdd t cac t aa t cpa t cac t aa t rch t rcs t clz t ohr t ohc t crp data valid-2 hi-z row address hi-z hi-z 20 t off column-1 row address column-2 t cprh column-3 t rrh t wpe t oho t wez data valid-1 t rcs t dzc t oez t wez data valid-3 hyper page mode read cycle ( hi-z control by w ) dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development ras-only refresh cycle t crp t asr t rah t ras t rc t asr t crp t rpc t rp row address row address hi-z 21 dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development cas before ras refresh cycle, extended refresh cycle * t ras t rc t asr t crp t rpc t rp row address t rc t ras t csr t chr t csr t rpc t cpn t rsr t rhr t rsr t rhr t rcs hi-z t oez t rp t chr t rez t rpc t rrh t ohr t ohc t oho t off 22 column address t rch dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development hidden refresh cycle (read) (note 33) t crp t asr t rah t rad t rcd t cah t rcs t ras t rc t chr t cac t aa t clz t rac t off t asr t rp row address data valid t ras t rc t rp t rsh t asc column address t ral t dzc t cdd hi-z t dzo t oea t orh t odd t oez hi-z t rrh hi-z 23 note 33 : early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. timing requirements and output state are the same as that of each cycle shown above. t rch t rdd t rez t ohr t ohc t oho row address dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development self refresh cycle * (note 30) t rpc t asr t rps t rpc t rass t csr t rch t rhr t oez t rp t rsr t chs row address t crp hi-z t off t rez t rrh t rcs t rdd t cdd t odd t ohr t ohc t oho 24 t cpn hi-z column address dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development test mode set cycle (note 34) t asr t rp t rpc t ras t csr t cpn t rch t whr t oez t rp t wsr row address t crp hi-z t off t rcs t chr t rc 25 the cycle is also avaiilable for initialization cycle, but in this case device enters test mode. the test mode function is initiated with a w and cas before ras cycle(wcbr cycle) as specified above timing diagram. the test mode function is terminated by either a cas before ras(cbr) refresh or a ras only refresh cycle. during the test mode, the device is internally organized as 4-bits wide (256-kilobytes deep) for each dq (input/output) port. no addressing of a 0 ,a 1 (column only) is required. during a write cycle, data on the each dq (input) pin is written in parallel into all 4-bits for each dq port and can be written independently for each dq port. during a read cycle, the each dq (output) pin indicates independently a high state if all 4-bits are equal, and a low state if any bits differ. during the test mode operation, a wcbr cycle is used to perform refresh. note 34 : t rpc column address dq 1 ~dq 4 (inputs) v ih v il v oh v ol ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas v ih v il v ih v il v ih v il v ih v il v ih v il
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development switching from self refresh operation to read/write operation. the time interval from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the first cbr refresh cycle during read/write operation period should be set within t snd (shown in table 2) note 30 : self refresh sequence two refreshing methods should be used properly depending on the low pulse width(t rass ) of ras signal during self refresh period. 1. distributed refresh during read/write operation (a) timing diagram t nsd t rass 3 100? t snd ras 26 switching from read/write operation to self refresh operation. the time interval from the falling edge of ras signal in the last cbr refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within t nsd (shown in table 2). 1.1 cbr distributed refresh definition of cbr distributed refresh (including extended refresh) the cbr distributed refresh performs more than 1024 constant period (125? max.) cbr cycles within 128ms. all combinations of nine row address signals (a 0 ~a 9 ) are selected during 1024 constant period (16? max.) ras only refresh cycles within 16.4ms. definition of ras only distributed refresh note: hidden refresh may be used instead of cbr refresh. ras/cas refresh may be used instead of ras only refresh. 1.2 ras only distributed refresh switching from read/write operation to self refresh operation. the time interval t nsd from the falling edge of ras signal in the last ras only refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within 16?. switching from self refresh operation to read/write operation. the time interval t snd from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the first cbr refresh cycle during read/write operation period should be set within 16?. read /write cycle self refresh cycle read /write cycle last refresh cycle first refresh cycle table 2 t nsd 16? t snd 16? t nsd 125? t snd 125? read/write cycle cbr distributed refresh ras only distributed refresh read/write self refresh self refresh read/write (b) definition of distributed refresh t ref t ref /1024 ras t ref /1024 refresh cycle read/write cycles read/write cycles refresh cycle refresh cycle
edo ( hyper page mode ) 4194304-bit ( 1048576-word by 4-bit ) dynamic ram m5m44405cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44405cj,tp-5,-5s:under development all combination of nine row address signals (a 0 ~a 9 ) are selected during 1024 continuous ras only refresh cycles within 16.4ms. switching from read/write operation to self refresh operation. the time interval ns from the falling edge of ras signal in the first cbr refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within 16.4ms. switching from self refresh operation to read/write operation. the time interval snob from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the last cbr refresh cycle during read/write operatio n period should be set within 16.4ms. t nsb t rass 3 100? t snb table 3 ras 16.4ms ras t nsb +t snb 16.4ms t nsb 16.4ms t snb 16.4ms 27 2. burst refresh during read/write operation (a) timing diagram read /write self refresh read /write last refresh cycles first refresh cycles refresh cycles 1024 cycles refresh cycles 1024 cycles read/write cycle cbr burst refresh ras only burst refresh read/write self refresh self refresh read/write (b) definition of burst refresh read/write cycles refresh cycles 1024cycles definition of cbr burst refresh the cbr burst refresh performs more than 1024 continuous cbr cycles within 16.4ms. definition of ras only burst refresh switching from read/write operation to self refresh operation. the time interval from the falling edge of ras signal in the first ras only refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within t nsb (shown in table 3). switching from self refresh operation to read/write operation. the time interval from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the last ras only refresh cycle during read/write operation period should be set within t snb (shown in table 3). 2.2 ras only burst refresh 2.1 cbr burst refresh

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